The Design Of Σ-△ Modulator And It's Application In Power Metering

In the last several decades or so, the technology of digital signal processing(DSP) have obtained very fast developing both on theory and practice. In spite of that DSP has the characteristics such as high reliability, flexibility and low cost, and it has substituted the traditional signal process manner, namely analog signal processing(ASP), the ASP and analog integrated circuits(IC) design weren't out of fashion, moreover,they are playing the unreplaceable role in some given situation. It reflects the contradiction between practical analog world and suppositional digital world. Nowadays, the request for processing speed is more and more high, and manufactural technics lead the transistor's channel length is increasingly reduced, all sorts of parasitic effects are becoming emergent. All mentioned above pushed the ic engineers in a state of anxiety. For these reasons, it is often said "high speed digital design is in fact analog design."Before embarking the DSP, the analog to digital conversion should be accomplished. Among the wide variety of analog to digital converter(ADC) architectures, pipelined and oversampled ∑ -Δ converters are the most suitable candidates to meet the needs of current. Although pipelined ADC are generally preferred for realizing high conversion rates, their sensitivity to component mismatch results in a significant increase in complexity and, potentially, power dissipation are envisioned if resolution beyond 14bits. So, the accuracy of pipelined ADC is not enough. By combining over-sampling and noise shaping, the ∑ - Δ ADC have achieved high accuracy, but the frequency of input analog signal which converted by it is not very high. Despite of this, in ∑ - Δ ADC, the front-end input analog signal is modulated to be high speed bit-streams by the ∑ - Δ modulator, and then using a digital low-pass decimation filter to attenuate the noise that has been pushed out-of-band.Because of this method, ∑ - Δ ADC is easy to integrated with very large scale digital circuits, the cost will be very economy. The ∑ - Δ modulator which belongs to analog circuit is a feedback architecture, it has good immunity to circuit's non-ideal effects. Compared to nyquist sampling, ovsampling cause the design of anti-aliasing filter to be an easy task. Depend on these merits mentioned above, the ∑ - Δ ADC is applied to many situations.The ∑ - Δ modulator's design was discussed in this thesis from system architectures to circuits' details. At the beginning, the second chapter introduced some fundamental concepts such as sampling, quantization and noise shaping. The various topology of ∑ - Δ modulator were explored in third chapter, including the basal first and second order, single stage single loop high order, multi-stage cascaded, as well as multi-bit. The fourth chapter looked into the implementation of ∑ - Δ modulator, including feedforward, feedback, integrator, operational amplifier(opamp)and comparator.The sorts of non-ideal effects were investigated in fifth chapter. For instance, sampling resistance's thermal noise,opamp's input refered noise, dc gain, bandwidth, slew rate, comparator's hys-tersis and offset, and so forth. In the thesis,the noise performance of the integrator which was treated as a whole was analysed. The analyse result was presented. A rather accurate settling process model of integrator was established.In the last chapter, as an example, a second order 2 - A modulator which applied to power metering was designed. The voltage and current obtained from power transmission wire are bipolar analog signal, however, the power metering chip is single supplied.The first, PMOS transistor should be used as sampling switch. If NMOS transistor is adopted, the input signal will be diode clamped when it is negative. Even though PMOS transistor are used for switching,while a negative analog input signal is applied, this PMOS transistor will not turn on since the lowest voltage of clock at the gate of the transistor is zero. One technique is to shift the voltage of the input signal.However, such level shifting voltage may tend to change with temperature and noise,unlike a more stable ground. An input buffer was designed to solve the problem in this thesis. It is built by little components, saving the area of the chip.