Design Of FRAM Cells And Arrays

Ferroelectric random access memory is a new non-volatile memory, inwhich ferroelectric material is applied in semiconductor technology. Becauseof the features of high density, high speed, low power consumption, increasedendurance and radiation hardness, ferroelectric memory is regarded as thepromising future memory, which has the potential to replace traditionalmemories, such as DRAM, EEPROM and FLASH.In this paper, the design method of FRAM cell and array are investigated.And based on the process condition, the process flow is designed and optimized;the fabricated FRAM cells is tested and analyzed.Firstly, the design and analysis of different memory cells are carried outunder a novel ferroelectric capacitor model using H-SPICE. Throughsimulation, the optimization of the storage capacitance, dummy cellcapacitance and bit line load capacitance is accomplished. Based on thesimulation results, a novel chain FRAM is proposed.Secondly, according to the practical process condition, the lithographicmasks and layout design rules are constituted. The layout of FRAM cells isdesigned. The fabricated FRAM cells are tested and analyzed to improve theperformance.Finally, design and optimization method of a 4 kb FRAM module areinvestigated, including periphery circuits, memory cell, read/write operation,memory array architecture etc.