IP Development Based On Video Processing System Platform

Nowadays digital video processing is a hot topic in academia and industry, with characteristics of huge data volume, high real time and complex algorithms. Based on SoPC technology and IP core reuse, FPGA embedded system is suitable as a solution for video processing system platform due to its powerful parallel computing ability and excellent event management ability. This paper aims to build a video processing system hardware platform based on FPGA embedded technology and focus on the development of several IP module.For hardware frame design of video processing system platform, peripheral hardware resources on FPGA development board are used. Besides, OpenRISC and video processing DSP are used as internal logic, as well as surrounding key IP modules which include memory controller IP modules and video stream receive/transmit IP module.Memory controller IP modules include SDRAM controller, SSRAM controller and SD card controller. Based on the work principle and user manual of each memory chip, RTL design method based on FSM is used for memory control. For design of SDRAM controller and SSRAM controller, the focus is to set each working status and define key timing parameters according to the timing diagram, in order to make data read/write operation comply with timing specifications. For SD card controller, precess state control, command operation control and SPI bus are designed based on the command-response mechanism of SD card protocol. Through functional verification, SDRAM controller and SSRAM controller realize correct single/burst data read/write functions at 100MHz clock and 150MHz clock respectively. For SD card controller, data block read/write function is achieved in SPI mode at 25MHz clock.Video stream receive/transmit IP module, along with corresponding chips, is responsible for video data processing before and after video processing algorithm, including detection and output of video stream format, pixel conversion between RGB space and YUV space and configuration for DVI receive/transmit chip. Existing video processing DSP is added between video stream receive/transmit module during FPGA verification and desired effect is achieved, which meanwhile verifies the functionality of the two modules.Finally, for the purpose of IP core integration, Wishbone bus interface design of SDRAM controller and SSRAM controller is discussed, which meets the timing specification of Wishbone bus interface.The IP modules developed in the paper are of well-defined functions and compact structure, with specific document and code, and easy for integration into video processing system platforms, while reducing the cost of system development.