Research And Implementation Of DFT/IDFT For LTE Uplink

In the past 30 years Mobile communication has the rapid development. LTE (Long Term Evolution) is put forward by 3GPP (3rd Generation Partnership Project), which is a new generation mobile communication standards after the third generation mobile communication. With OFDMA (Orthogonal Frequency Division Multiple Access) and multi-antenna as the main technical basis, LTE can meet the lower latency, higher user data rates, increased system capacity and coverage, lower operating costs and other requirements.LTE downlink uses OFDMA multi-access transmission, but in order to reduce the power consumption of mobile terminal, the uplink uses SC_FDMA (Signal Carrier Frequency Division Multiple Access) multi-access transmission mode. Using DFT (Discrete Fourier Transform) pre-coding before the OFDMA is an important difference between LTE uplink SC_FDMA and downlink OFDMA. In order to dynamic distribution terminal resources, the 3GPP provisions the DFT points are variable, the DFT pre-coding including 35 modes DFT, which are non-power of 2 and are the key characteristics of single-carrier. Although there are many studies for the DFT, supports configurable, non-power of 2 and high-throughput DFT design has been always a challenge, this study is very practical.According to the agreement, this paper researched and completed a FPGA (Field-Programmable Gate Array) implementation for DFT/IDFT, which work on a high clock frequency and reach the LTE system clock requirements, at the same time meeting the treatment time requirements, and achieve high-speed DFT operation. The DFT/IDFT not only meets the 35 modes DFT/IDFT in the LTE uplink SC_FDMA, but also meets 1536 points DFT/IDFT when the system bandwidth is 15MHz. This design can complete all the DFT/IDFT operations which are non-power of 2 in the LTE system, and can be used in actual LTE projects.This paper research the various DFT algorithms, then give a design algorithm. According to the time requirements required by system, using compromise of time and area, this paper proposed a framework for the DFT/IDFT. In the process,this design optimization the WFTA (Winagrad Fourier Transform Algorithm) butterfly operation unit, and share some of the butterfly unit in order to reduce the number of multiply-add operations, use the feature of twiddle factor to simplify the storage, use a reasonable way to process data to meet the accuracy requirements of fixed-point algorithm. Use C floating-point and C fixed-point model to compare with matlab model to show the performance of structure. Finally, use RTL (Register Transfer Level) simulation model results to compare with the C fixed-point model to verify the correctness of hardware logic, and FPGA synthesis results are given to provide a practical reference for the DFT/IDFT design in the LTE.