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Design And Implementation Of FPGA-in-the-loop Simulation With MATLAB And FPGA For Polar Code Decoder

Posted on:2022-08-11Degree:MasterType:Thesis
Country:ChinaCandidate:Q H YangFull Text:PDF
GTID:2518306572985759Subject:Electronics and Communications Engineering
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Polar code is a channel coding method that has been theoretically proven to achieve channel capacity.Once it was proposed,it has attracted widespread attention from academia and industry,and has become the control channel coding scheme in the 5G enhanced Mobile Broadband(e MBB)scenario.Based on the simulation analysis of the Successive Cancellation List(SCL)decoding algorithm of polar code,this thesis implements the decoding algorithm on FPGA,then packages it as Advanced e Xtensible Interface(AXI)IP.The FPGA-in-the-Loop(FIL)framework provided by MATLAB can be used to test the FPGA decoder of polar code on actual hardware,which provides decoding incentive and receives decoding feedback.But the framework has low efficiency of co-simulation and poor compatibility of hardware platform.For faster,more stable and accurate co-simulation of FPGA decoder with AXI interface,a co-simulation framework for AXI interface is designed in this thesis.And two cosimulation schemes are designed and implemented based on this framework,which are respectively based on ethernet and PCIe connection.The co-simulation scheme based on ethernet connection uses ARM to store and forward data between MATLAB and FPGA,and uses mixed programming of MATLAB and C programming language to accelerate the development.In the co-simulation scheme based on the PCIe connection,the FPGA logic development,the PCIe driver and the C program are completed,and the dynamic link library is generated by the mixed compilation of the C program for MATLAB to call,so as to implement the interaction between MATLAB and FPGA decoder.The two co-simulation schemes of the decoder and MATLAB FIL framework are tested on Xilinx VC707 and ZC706 development boards.The test results show that the simulation speeds of the two co-simulation schemes in this thesis are 70 times and 166 times that of the MATLAB FIL framework.And the two co-simulation schemes in this thesis can guarantee stable operation when the simulation data volume reaches one million frames.What's more,results of the two co-simulation schemes are very close to the theoretical simulation results of SCL decoding algorithm.
Keywords/Search Tags:Polar code, Successive Cancellation List decoding, FPGA, co-simulation, FPGA-in-the-loop
PDF Full Text Request
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