SSTL Interface Circuit Design Of DDR SDRAM Phy

The memory is used widely in modern electronic system design, and the access speed and capacity are also required to meet the needs of DDR SDRAM. The frequency of DDR SDRAM interface circuit is a few hundred MHZ as the inner-core operating frequency has reached several GHz, so the interface circuit technology has become a bottleneck in the rapid development of integrated circuits. In order to solve the problem, a SSTL standard between the DDR SDRAM and the inner-core has appeared. Based on 0.13μm standard CMOS technology, the SSTL interface circuit that the operating frequency is 400MH should be designed and used in memory controller.First, this paper introduces the background and relevant theories of SSTL interface circuit, and then presents a SSTL interface circuit designs. The SSTL I/O buffer and SSTL timing control circuit are two parts of SSTL interface circuit. SSTL I/O buffer contains input buffer, output buffer and a terminal ODT. A test function and static electricity protection circuit are designed in the input buffer, and current drive mode is used to improve the circuit's operating frequency and drive capability of output buffer. In order to prevent the output signal reflection, a terminal ODT is integrated in the I/O buffer chip. SSTL timing control circuit contains two sub-modules which are the data and control ling channel, adoption of symmetry matching circuit design can improve the accuracy of timing control. Besides, the output and internal power supply circuit are separated, to avoid crosstalk between the power supplies and also reduce circuit power consumption. Finally, the results of SSTL interface circuit simulation and post-layout simulation show that the performance of our design is stable, and the driving ability can also meet the requirements of SSTL standard under 400MH with low power consumption.