Rearch And Implementation About Verification For USB IP's Physical Layer Interface

As the ASIC design size increase,the verification is one of the most important phase of the pre-silicon design. Many new verification theories have emerged one after another, but these theories can't be used directly on projects.Verification pertains to engineering experience,how to choose the appropriate verification method for each product to abtain the greatest efficiency remains a topic.USB(Universal Serial Bus)is a fast,bi-directional,synchronization,serial interface. USB IP includes link layer and physical layer which is an important module of the SOC project of GuoWei Electronic Company.TheUSB Physical Layer Interface(USB PHY) that bases on UTMI(USB Transceiver Macrocell Interface) specification is a hard core. The USB PHY connects the hub and the USB controller,the main functions of it is convert serial data to parallel data/convert parallel data to serial data,bit stuff/unstuffy and NRZI encode/decode.The verification that bases on FPGA platform is flexible, easily used and reusable.So this paper use the FPGA platform as testbench,the design of stimulus bases on TBV(Transaction-Based Verification) and adopt FPGA logic to implement the automatic response of the function verification.The author advances the verification method,designs and implements a part of software and FPGA logic,conducts the functional test, the reliability test and the eye diagram test, at last analyses the test report.At result the IP core failed the test on some items but after modifying the layout,the IP core's performance enhances much.The result proves that the verification is effective.