The Design Of Master-slave DLL For DDR2 SDRAM Controller In Phy

Delay-Locked Loop clock, with the advantages of accurate clock positioning, anti-shake capability and quick locking ability, has been widely used in a variety of timing systems. With the development of memory technology, there have been more strict demands of clock jitter and bias for the memory controller, which also gives the DLL a more and more important position in DDR controller application fields, and makes DLL widely used in clock synchronization, harmonic and multi-phase clock generator and other circuits for high-speed memory interfaces.Based on the theoretical study of DDR2 controller and DLL, this essay describes the design and implementation of a Master and Slaver of Delay-Locked Loop applied for the DDR2 controller. The DLL works at the frequency of 400MHz, with the full functionalities and good performance. It well meets the clock requirements of the physical layer of DDR2 controller. The design implemented a four-phase voltage-controlled delay line and make four-phase delay clock, working in the operating frequency, through a full custom designing and the 0.13 ? m CMOS process. The accurate clocks supplied by DLL sample the data from single data rate to double data rate when writing data to SDRAM. Differential voltage-controlled delay line was used to improve the performance of voltage controlled delay line. Simulation results showed that the DLL functioned correctly with good performance. Additionally, fine-tuning and relative testing module were added in the design to facilitate the adjustment and testing. Master and Slaver of Delay-Locked Loop also uses the same structure to reduce design complexity and the circuit area, which makes it easy to be integrated.