An Analytical Model Driven Framework For Efficient And Accurate Soft Error Analysis In Processors

With the scaling technology, soft error induced bit upsets dominate the failure of processor execution. To get a good tradeoff between design cost(e.g., area) and reliability, the accurate and efficient estimation methods are critical to guide the optimal design of reliable processors.So far, the challenges of soft error estimation mainly include three aspects: extreme tradeoff between estimation accuracy and efficiency, increasing complexity due to increasing Multi-Cell Upsets(MCU) ratio in total soft errors, and no good solution applied into novel many-core processor. In this paper, we address these problems via an analytical model driven framework for the accurate and efficient soft error analysis:Firstly, the effective soft error analysis is proposed for more accurate and more efficient estimation, through exploiting and exploring the error masking effects comprehensively. The key idea is to design a flexible Probabilistic Graphical Model(PGM) based methodology to achieve three different accuracy-efficiency tradeoffs based on typical ACE(Architectural Correct Execution) analysis for different types of applications: i) MEA-PGM-FO is a simple version of PGM methodology, which captures the first-order masking effects fast and provides a tighter upper bound over ACE. And the results demonstrate that, compared the state-of-the-art, it can achieve a more accurate estimation, up to 45.96% and on average 8.48%, while still keeping 52 x speedup over fault injection(FI). The high reliability design like in automobile products needs such a solution; ii) MEA-PGM-HMM adopts a heuristically mechanical model for higher accuracy. The results show that, the approximation based PGM method can provide a more accurate estimation, up to 98.18% and on average 79.14% with 59 x speedup. The low reliability requirements like stream processors can use MEA-PGM-HMM well; iii) MEA-PGM-HO uses a truncated VE(Variable Elimination) inference to optimize both estimation accuracy and efficiency. The simulation results point that the efficient proposed approach can get a near-perfect value, up to 95%, and on average 87.28% with 43.78 x speedup. This method is more suitiable for the high reliable areaspace or airplane environment. In a summary, the flexible PGM driven methodology meets the estimation accuracy-efficiency tradeoffs very well.Next, the proposed Hi Bo M aims at the MCU estimation issue. On one hand, Hi Bo M makes good use of the efficient SBU estimation result to calculate the maximum and minmum value in a boundary model; on the other hand, the histogram based simulation partition is proposed to shrink the estimation range. The results verify that the proposed MCU considered estimation achieves 44.67~94.6x speedup over accurate fault injection. Therefore, Hi Bo M addresses MCU estimation issue very well.Finally, we also exploit the soft error estimation methods in a many-core processor. From the network architecture and processor component perspectives, we propose two methods respectively: Simutanious fault injection based on PRP measurement and Accelerated fault injection method based on pre-analysis(MEPA). The former only requires one or several simulations to achieve fast estimation and is verified by the reliable-aware link addition schemes; while the latter provides 5x speedup over typical FI via pre-analyzing the predictable information, including application communication characteristics, inherent masking and the error recovey of reliable solution and so on.All in all, the paper designs an analytical model driven methdology for accurate and efficient soft error analysis in processors. So that the current challenges, including accuracy-efficiency tradeoff, complex fault model and novel processor architecture, are addressed well by the instanced methods like MEA-PGM-FO、MEA-PGM-HMM、MEA-PGM-HO、Hi Bo M、PRP and MEPA.