Design And Verification Of BCH Encoder And Decoder

In the times of digital technique development, NAND flash memory have developed rapidly due to its nonvolatile, erasability and lower price per bit, and widely applied in the handheld devices, such as digital camera, Palm computer and so on. Although NAND flash memory has been transformed from traditional SLC into MLC, MLC NAND flash memory device needs heightened ECC. Thus, the implementation of advanced ECC algorithm brings great challenge to the designing of embedded processor.In this paper, BCH code which can correct 24 bit errors is adopted in order to correct random errors of memory chip. BCH codes can correct two or more errors with the advantages of easy coding, decoding implemented and so on, and well adapted to the characteristics of the random errors of NAND type memory system. Therefore, it is of great significance to research on coding and decoding algorithms for binary BCH codes.This article first introduces the development of present situation of NAND flash memory and the development process of ECC checkout, and describes the background knowledge and theoretical basis of BCH codes. Then it gives in detail the coding and decoding algorithm, the capability of error correction and the hardware design and implement of 24 bit BCH codes, with an emphasis on the research of the representative BM algorithm. Besides, methods of software and hardware environment construction and analysis of experiment results are shown with an introduction of the popular OVM verification methodology. Practice has proved that the IP core can correct data within 24 bits effectively. A summation is made to generalize the work in this paper, and the prospect of the further study is put forward.