The Research Of Catapult SL Synthesis

The scale of FPGA is larger and larger,it's internal resource is more and more ,and the using is more complex.Using the traditional flow,the designer have to translate the C/C++ code to register translation level code,the process will cost much more time,and very easily making mistakes.Otherwise,debugging the RTL code will cost a lot of time.Those reasons above make the designing period longer and longer.So a new and more efficient flow is needed to meet the complex designing.The Catapult SL Synthesis of Mentor Graphics Corporation is an algorithm synthesis tool.Using Catapult SL Synthesis,designers can translate their untime C/C++ code to RTL netlist.It saves the time of writing and degbuging the RTL code.In this paper,I will design an FIR filter using the traditional flow and the Catapult flow.By comparing the result of the two flows to research the advance of Catapult SL Synthesis.In thies paper,I will describe the FIR filter with VHDL in tranditional flow and describe FIR filter with C++ in Catapult flow.