Research Of Image Processing Acelerator Based On FPGA

21st century is the epoch of electronic information, with the rapid development of multimedia technology in the digital image processing that is widely applied to various industries, such as security, atmosphere, transportation, aviation, industrial detection, etc.With increasing data in image processing, the adoption of the software scheme to proces images has been unable to meet the needs of real-time, and microelectronic technology is develop to fast, efficient, high integration, high reliability. It makes digital image processing system have more advantage which is based on hardware platform. Field programmable gate array(FPGA) is a kind of ideal hardware of solutions, and image processing based on FPGA accelerator research become a hot topic at home and abroad now.Based on the FPGA platform, adopting Verilog HDL which is a language of hardware description, research a configurable images accelerators to achieve arbitrary image of median filter and edge detection within the 1024 *(a natural number) resolution ratio and 256 grayscale.Using the SPI bus protocol, the external CPU can read and write the custom register in FPGA, set the parameters of image size and model, complete the different needs of median filter and edge detection processing, store the processed data in the asynchronous FIFO memory at the same time. In design, follow the principle of enchange of speed and area and the structure of water, parallelism of mining algorithm,the use of measure to perfect algorithm and temporal constraint. It can improve the speed of top-level module to achieve the speed of image processing, reach the effect of acceleration.The design of image processing accelerator is based on Quartus II 14.0 development environment which is designed by Altera, the simulation is run under Modelsim SE 10.2of Mentor. Comprehensive and simulation results show that the design can better complete the image processing function of the set, the highest frequency can reach128.8Mhz, image data processing flow rate up to 1Gbps, for a 8 bit gray image of800*600 resolution of median filtering and edge detection processing, can reach up to260 frames per second.This paper make the exploratory attempt for study of the application of FPGA in the image processing hardware accelerator, put forward a kind of image processing accelerator research mentality and the realization method. Designed a image processing accelerator based on FPGA that data processing flow up to 1Gbps. This study have the positive significance and reference value to the research of image processing accelerator based on FPGA.