Study Of The Power Consumption Of A Digital-front-end Using Random Sampling

The theory of digital signal processing, based on Shannon uniform sampling theorem, is perfect and has been applied widely in various fields. But, in the practical engineering, the disadvantages of Shannon sampling theorem result in some problems. This paper illuminates the theory and application of non-uniform sampling, and develops a hardware system to implement non-uniform sampling based on FPGA.Recently, digital front-end is one of the most important parts in mobile terminal devices. Decreasing power consumption and sampling frequency in Digital front-end have considerably theoretical and practical significances. In this article, we propose to using FPGA to design a circuit which can generate the random clock simply and efficiently. Then we use this random clock as the working clock of ADC, and the random clock can sample the signal randomly and decrease the power consumption of the ADC or Digital front-end efficiently. By the simulation and experiment results, we validate that the design of circuit in this article can generate highly randomly clock signal, and we also proved that greater randomness of clock is, the lower power consumption of ADC has.The article is an introduction first.Simple theory and sample method for introducing a sample;Combined to outline the theory of nonuniform sample and it deveolps present condition at home and abroad, then introduces the foundation theory of not-even sample in detail in the second fraction.Use in the third fraction MATLAB carried on to imitate vs even sample and non-blance sample really with frequency chart analytical, carried on a verification to the reliability of not-even sample.Number the four-part deci is a textual point fraction.In detail introduced whole immediately the hardware design and realize of the clock occurrence mold mass, software design and realize.Is the design frame of the whole hardware system first chart;Then introduced the hardware design of FPGA and ADC connecting orifice;Finally carry on software compilation and the realize of function to FPGA, and vs ADC the power dissipation progress while adopting random clock and even clock contrast.The end is a textual end language.Tallied up the related contents of this topic, and aftertime's search direction.