Design Of Unified Time Subsystem Of Distributed Sound Source Localization System

Unified time system provides time reference for coordinating various sets of measurement & control equipments to work together. This system generated from the area such as modern aerospace test,shooting and conventional weapons test. With the development of science and technology, unified time system was widely used in several engineering & research fields such as modern communication, navigation, electric power dispatching, sound source localization, geodesy, earthquake, transportation, etc. In this thesis, we designed an unified time subsystems of the distributed sound source localization system which can be used for military project.In this paper, based on the requirements of sound source localization,the influence of the unified time system on the positioning accurary was analyzed by simulation. Several common unified time protocols were introduced such as NTP, PTP, IRIG etc. IRIG-B protocol was chose as the time synchronization protocol of distributed source localization system according to the application background and performance requirements. Unified time subsystem consisted of national time reference station,timing set, time and frequency calibration Receiver, frequency standard, time code generator, time decoder, among them the time encoder and the time decoder were the emphasis of the design. Firstly, the thesis dissertated emphatically the structure of IRIG-B coding, the principle and the overall structure of encoder & decoder. Secondly, the IRIG-B encoder & decoder circuits were implemented by adopting FPGA technology and corresponding peripheral circuits were designed. Thirdly, several design methods of common programmable device were introduced. And then, we presented circuit design and simulation of the encoder with VHDL language, which includes clock pulse circuit module, frequency divider, BCD coding module, IRIG-B coding module, frequency synthesizer module, DA conversion control module and so on. Fourthly, PLL module which was used to stabilize frequency, decoding module, storage control module, man-computer interface module(LCD and key board), serial control module and decoder module were designed and the simulation was given in decoding aspect. Finally, this thesis sumed up debugging criterion and experience in allusion to many problem during the design and the debug process based on the FPGA.