Study On The Gate Leakage Current Of Uitra-thin MOS Devices

As dimensions of MOSFET are scaling down and the thickness of gate oxide is decreased, the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime. This dissertation deeply and systematically studies the physical mechanism of gate leakage current and the related reliability issues in MOSFET’s fabricated by90nm CMOS process. The two basic elements in the dissertation are the direct-tunneling (DT) current in MOSFETs with ultra-thin gate oxide and the stress induced leakage current (SILC) under various stresses in DT region.Firstly, the dissertation begins with the investigation of the DT current in MOSFETs with ultra-thin gate oxide. The physical mechanism of tunneling in MOS is discussed firstly. Some related issues about the DT including Quantum-Mechanical effect, polysilicon gate depletion effect and tunneling current components are discussed. DT current in MOSFET with1.4nm gate oxide fabricated by90nm CMOS process is studied. Law of variation of DT current with channel length, channel width, measuring voltage, drain bias and reverse substrate bias is analyzed. Edge direct-tunneling (EDT) current in MOSFET with1.4nm gate oxide biased in conventional off-state is also tested and studied. By using simulation method, the impact of DT gate leakage current on CMOS logic circuits is studied.The degradation characteristics and gate leakage currents of uniform injection stresses in MOSFETs with ultra-thin gate oxide are studied. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V,h degradation in NMOSFETs during positive and negative DT stresses. A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress. A comparative study of SILC characteristics and mechanisms in NMOSFETs with ultra-thin gate oxide under constant-gate-voltage (CGV) stress and substrate-hot-electron (SHE) stress is made. We demonstrate that the oxide damaged by hot electrons shows different breakdown characteristics compared with the case CGV stress experiments. The SILC characteristics and mechanisms in PMOSFETs with ultra-thin gate under substrate-hot-hole (SHH) stress are also studied. During SHH stress, the hot holes inject the oxide and break the Si-O bonds.The breakage of the Si-O bond causes the change of the structure of the oxide network. The accumulation of the damage finally leads to the oxide breakdown.The degradation characteristics and gate leakage currents of conventional off-state stresses in NMOSFETs with ultra-thin gate oxide are studied. The behaviors of the GIDL stress in LDD NMOSFET are studied. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. A likely mechanism is presented to explain the origin of SILC during GIDL stress. The behaviors of the Snapback stress in LDD NMOSFET are studied in ultra-short and ultra-thin LDD NMOSFET’s. The avalanche hot holes and electrons together inject into oxide during Snapback stress, much interface states and neutral electron traps are generated. The increase of the oxide neutral electron traps can cause the increase of SILC and the appearance of soft breakdown.The degradation characteristics and gate leakage currents of hot carrier stresses in NMOSFETs with ultra-thin gate oxide are studied. The behaviors of low gate voltage (LGV) and peak substrate current (Isub,max) stresses are studied in ultra-short and ultra-thin LDD NMOSFET. It is confirmed that the LGV stress is still the hole-injection stress in ultrashort and ultrathin LDD NMOSFET but Isub,max is a both electron-and hole-injection stress. It is found experimentally that there is a linear correlation between the degradation of SILC and that of V,h during the two stresses. It can be concluded that the origin of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFET under the two stresses. The behaviors of the channel hot electron (CHE) stress at high temperature in LDD NMOSFET are studied and it is found that there is a linear correlation between SILC degradation and Vth degradation in NMOSFET during CHE stress. The mechanism of the combined effect of oxide trapped negative charges and interface traps is used to explain the origin of SILC during CHE stress at high temperature.