Studies On The High-K Gate Dielectrics MOSFET And Related Device Effects

As the dimensions of CMOS devices continues to scale down, the gate oxide thickness reduces greatly. The increased leakage current has become the dominant reliability for nonvolatile memories and complementary metal-oxide-semiconductor (CMOS) logic circuits for low power and portable application. For the ultra-thin oxide (<30 (?)), new phenomenon for concern in the electrical characteristic and the reliability of the gate oxide include increased poly-silicon gate depletion, quantum mechanical because of the poly depletion and quantum effects, high direct tunneling induced gate leakage current.Based on the above issues, the combination of approaches of theoretical analysis, numerical simulation and experiment is used to do the following research. (1) we examine the direct tunneling of MOSFET and investigate the direct tunneling current from the P-type (100) substrate to gate and the edge direct tunneling from the gate overlap to the source and drain extension in nano-scale MOSFET with low V_dd independently. Electron concentration distribution use Fermi-Dirac statistics, a modified WKB approximation allows for the transmission probability in numerical computation. In addition, two methods are introduced to suppress the edge direct tunneling current—polyreoxidation and high K gate dielectrics (Seen in Chapter 2). (2) High K gate dielectrics can lead to fringe induced barrier lowering (FIBL), so we describe the physics behind the FIBL effect in Chapter 3. (3) We investigate the off state leakage current in Chapter 4, the conventional gate induced drain leakage current (I_GIDL), subthreshold leakage current (I_SUB), band-to-band tunneling current (I_BTBT) and the edge direct tunneling current are compared. (4) We systematically investigated the characteristics of HfO₂ and incorporation of N and La in HfO₂ in Chapter 5.This dissertation obtains the following achievements. (1) For nMOSFET, the edge direct tunneling current dominates the gate current and it prevails over the I_gc for V_FB g <0 V. (2) fringing induced barrier lowering arises when A>25, which can lead to significant off-state leakage current. (3) A large increase in off-state leakage current occurs for smaller devices due to increase in edge direct tunneling current at high V_dd, which can lead to large power dissipation and can be reduced by high K gate dielectrics. (4) This paper indicates that edge direct tunneling and FIBL should be considered together to choose high K gate dielectrics in order to reduce off state leakage current for the first time. (5) This paper also examined HfSiON and HfLaO gate dielectrics and the I_edt with them is 2-5 orders of magnitude lower than that of SiO₂ and FIBL is small. These achievements can help to realize and understand the related device effect of nano-scale MOSFET to a great extent and they provide novel valuable guidance for choosing the new gate dielectrics.