SpaceWire Router Design And Analysis Based On FPGA

With the advances in space technology, and significant increase in the types and quantities of satellite equipment, A new bus technology with high speed, scalable, low power consumption, and low cost is needed to meet requirements of data handling. SpaceWire is a new data communication protocol, which is serial, high speed, point to point, bi directional, full duplex, with the advantages of high performance, low cost, fault tolerant network structure and so on. As a new generation of high speed bus standard special for aerospace applications, it is widely used by space agencies and industry like ESA, NASA and so on. But in China, the study on this subject is still in the early stage. The work of this paper is SpaceWire router design related research.This paper embarks from the SpaceWire protocol, introduces and discusses SpaceWire router principle and characteristic in detail. A SpaceWire router design is also proposed in this paper which supports four SpaceWire interfaces and an external interface for cascading. This design includes two modules: SpaceWire router interface circuit and routing switch. This router is designed by hardware description language, and realized on FPGA platforms, according to the top down design principle of design. Receive FIFO and send FIFO used to cach data are added in the interface circuit. At the same time EDAC technology and fault tolerant state machine structure are used to improve radiation resistance. And we design a low delay, non blocking, 5 ports Crossbar Switch which based on virtual channel buffer and Wormhole Routing.