Design And Verification Of Spacewire Router Based On The FPGA

SpaceWire bus is a newer specialized communication standard for aerospace applications, which islaunched by the European Space Agency (ESA). It is based on IEEE1355and ANSI/TIA/EIA-644commercial standards. Its main features are: serial, bidirectional full-duplex, all-digital, high-speed(200MHz) with the router topology. Because of these advantages, it has a broad application prospectin the aerospace industry.Based on the study of SpaceWire protocol, the design and verification of the SpaceWire router areaccomplished in this paper. The main work includes:(1) On the basis of the analysis and comparison of the various bus used in aerospace, researchstatus and principles of SpaceWire are discussed in the paper. The bus protocol is divided into thephysical layer, the signal layer, the character layer, the exchange layer, packet layer and network layer.Each layer is studied detail to serve as the design reference of the router.(2) In this paper, a four-port and full duplex router IP core is designed. And the nodes and routingunits of the IP core are designed and simulated respectively.For the design of the nodes, a hierarchical method is used. The nodes are divided into Rx, Tx,Rx_FIFO, Tx_FIFO and FSM modules. The FCT flow is utilized to control the nodes’ datatransmission, which is easier and faster than TCP and UDP protocols. And the nodes’ clock andDS-decoded clock are synchronized based on the two-level trigger method.As for the routing units, a non-blocking algorithm based on output port dislocation and time sliceround-robin scheduling cell matrix is proposed to avoid the priority discrimination of input and outputports, simplify the algorithm, reduce the hardware cost and shorten the time delay. Meanwhile, inorder to avoid circuit transmission errors which are caused by SEUs incluced by space radiation, thefault tolerance mechanism is added into the cell unit. HanMing coding is encoded by the data, whichcan correct one error and detect two errors. When errors are detected, the dynamic partialreconfiguration approach for the single cell can achieve triple modular redundancy and Partition Pin isused to replace traditional bus macro as a transfer hub for static modules and dynamic modules. Onthe one hand, the dynamic triple modular redundancy reconfiguration can improve the reliability ofdata. And on the other hand, it can reduce the consumption of hardware resources.(3) On the Xilinx Virtex5development board, EDK is used to set up the hardware platform. TheSpaceWire router IP core is hung on the PLB bus with MicroBlaze core as the processor. And finallythe communication rate can reach75Mbps.