Router Design And Network Performance Analysis Based On 3×3 NoC

As a new on-chip communication solution, NoC(Network-on-Chip) technology is presented to solve the great difficulties that traditional SoC(System-on-Chip) technology based on bus structure has encountered. As the core element of NoC communication node, the router has a great influence on the performance of NoC.After explaining various key technologies of NoC, this paper designs a Port-Asynchronous-Inside-Synchronous router architecture based on 2D Mesh topology, XY dimension-ordered routing algorithm, wormhole switch mechanism and Round-Robin arbitration strategy. The paper introduces design methods of sub-modules that constitutes a router in detail, then proves that the router is able to perform its function correctly; furthermore, analyzes the effect of buffer resource size setting on router performance through FPGA and ASIC implementation. On the basis of this, after defining the sequential relationship among the communication node I/Os, the paper design a 3×3 NoC communication network that combines router and NI(Network Interface), then establishes a simulation and test platform to verify that it can satisfy communication requirements under the conditions of different network statuses and complex clock signals; besides, based on these test results, illustrates the influence of router buffer resource on network performance, such as throughput and latency; finally draws a conclusion that buffer resource size setting should come up with a compromise between performance and cost.