The Key Technology Of Asynchronous Routing Node In Network On Chip

With the continual development of nanoscale CMOS integrate circuit technology and System on Chip (SoC) technology, on-chip multi-processors (CMPs) have already become multi-IP cores and heterogeneous IP cores, while the shared bus architecture applied widely in the SoC presently gradually becomes the main bottleneck which restrict the system performance of CMP and can't meet the requirement of SoC. Therefore, the interconnection network is used for the SoC designs in order to resolve the communication between the on chip components, namely Network on Chip (NoC). NoC overcomes the poor scalability of bus architecture, provides a viable on-chip communication mechanisms for the age of billions transistors and has a high reusability as well as on-chip communication structure and services. As for NoC, router designs are the key to realize high performance, but due to the defects of synchronous circuits in power consumption and latencies, it must adopt the asynchronous and other new ones to achieve.The thesis investigates the key technology of asynchronous routing node in network on chip systematically.First of all, present the basic asynchronous circuit cells of the router, such as C-element, Muller pipe, MUX etc, and discuss their handshake protocols, configuration and design rules in detail. The introduction of static virtual channel (VC) effectively resolve the link ports competition caused by data flits and the congestion caused by competition in the router, improve the system throughput, but when there are more input ports, it will be one of the main parameters which restrict the chip area and power consumption, therefore, we discuss how to allocate VC reasonably from dynamic aspect.Secondly, based on the traditional crossbar switch structure, talk over the adaptive-bandwidth, high-speed, low-power crossbar structure, then recommend the crossbar structures and their scheduling algorithm according to the kinds of queuing mechanism, bat around the buffered crossbar and partially buffered crossbar switch architecture and principle, present the RR circuit fabric verified and simulated under the SMIC 0.18μm CMOS technology.Finally, propose a fully asynchronous delay-insensitive arbiter with virtual channel which selects the arbitration mechanism, known as priority authorization and ordered authorization by detecting the input situation of VC, effectively avoid the deadlock and congestion. The use of threshold gate devices makes the arbiter delay insensitive, the advantages of the arbiter such as dynamic variable of the arbiter priority, high scalability etc, make it satisfy the needs of communication of multi-service NoC.