Research On Arbiter PUF Circuit Based On Bit Self-test And FPGA Implementation

The security problems of embedded devices are becoming increasingly prominent,and the security of the chip as the"core"of embedded devices is becoming more and more important.New attackers can use physical detection and other methods to directly crack the key inside the chip,which brings great security threats to the system.Physical Unclonable Functions?PUF?is a new type of hardware security technology that can use Challenge Reponse Pairs?CRPs?to generate keys.The corresponding relationship between CRPs is only determined by some physical differences in the manufacturing process of individual equipment,so it cannot be predicted to be cloned,so it is implemented as a hardware function that depends on the characteristics of the chip..However,due to the special structure of the PUF circuit,its output response is susceptible to environmental factors such as temperature and voltage,and its reliability is not high.It is necessary to use various error correction mechanisms to extract stable keys from noisy data.However,the introduction of error correction mechanism will bring huge overhead and potential security risks.Therefore,this paper proposes an Arbiter PUF circuit?BST-APUF?based on bit self-test,which greatly improves the reliability of the PUF output and avoids the use of error correction mechanisms.The main research contents of this article include:?1?Introduce the concept of PUF circuit and its stimulus response pair,and analyze the PUF evaluation indicators?reliability,uniqueness,bias?;Finally,the structure and performance of common PUF circuits are elaborated and analyzed The advantages and disadvantages of Arbiter PUF are finally determined as the research object of this article.?2?The traditional Arbiter PUF circuit is designed and implemented on FPGA,and its output reliability,uniqueness and bias are evaluated.On this basis,the factors affecting the reliability of the Arbiter PUF circuit are analyzed,and a general bit self-test reliability enhancement strategy is proposed.By adding a self-test module to the PUF circuit,the strength of the deviation signal that generates the response is automatically detected.And generate a flag to mark the output reliability.?3?A Bit Self-Check Reliability Enhancement Circuit?BST-APUF?is implemented for Arbiter PUF circuit design.A delay detection circuit is embedded in the Arbiter PUF circuit to automatically detect the delay difference of each PUF response,and the response with a large delay difference is marked as reliable by the reliability flag bit,and the subsequent circuit can select a robust response to construct the secret key.This paper implements BST-APUF on Xlinx Artix7 FPGA.The test results show that the bit error rate?BER?of the selected response is less than 10^-9,the bias is 50.3%,and the uniqueness is 49.1%,which has good performance.Therefore,BST-APUF can be directly used for key generation without any error correction mechanism.