Design And Implementation Of On Chip Bus In Network Processor Based On Split Transaction

With the development of VLSI and semiconductor manufacture technics, SoC (System on a Chip) is applied to various fields more and more widely.The bus architectures which are transplant from broad systems and ASIC chips can not meet requirements of SoC.Successful on-chip bus can alleviate designers'efforts exerting on IP blocks integration and can make components efficiently communicate with each other.In this paper, a bus architecture which is of high throughput and low bus latency, is presented for the heterogeneous multi-core network processor-XDNP. This bus architecture use two main layers to realize, is divided into the control plane buses and the data plane buses. The bus connection of the data plane buses is based on the split transaction. Meanwhile, a bus arbiter based on mixed priority arbitration algorithm for this bus structure is also presented in this paper, which ensures that the use rights of the bus are fair and prior. The control plane buses mainly consist of two parts: AHB bus and PLB-AHB bus bridge. By the PLB-AHB bus bridge, the communication between a processor with PLB bus interface and the devices with AHB bus interface is achieved. The purpose of design the PLB-AHB bus bridge is to make the network processor system with AHB bus interface could be tested in the Xilinx FPGA board.We use a method of combining simulation verification and assertions verification (SVA), to further ensure the correctness of the design module. At the same time, the advantage of assertion that it can quickly find and locate the design flaws is improving verification efficiency. When functional verification of the bus is completed, this paper built a platform for performance comparison, by which, come to the conclusion that compared to AHB bus architecture, the bus architecture this paper presented has a 2.3 times improvement in throughput and 45% decrease in communication latency. And the throughput of the system adopted this bus architecture can achieve up to 5.8Gbps.Finally, we mapped the design module to TSMC 0.13 um technology through 'Synopsys Design Compiler'. The delay of design module is 2.97 ns, which is able to meet the design requirements in design specifications about that the target frequency must not lower than 232MHz .