Study On Digital Channelized Receiver Based On FPGA

Along with the development of communication technology, it requires, in modern communication recon system, not only wide input bandwidth, high sensitivity and resolution, large dynamic range and the ability of processing much more signals simultaneously, but also can be competent for the modern high dense signal environment, and real-time or quasi-realtime processing plenty of information.In this paper, we mainly studies the efficient architecture of digital channelized receiver. According to the demand of actual engineering, we also make related technical research on FPGA realizing. First of all, base on the basic theory of broadcast digital receivers, the efficient structure of digital channelized receiver based on multiphase DFT has been discussed in depth. Aiming at the problems, such as blind area, channel fuzzy and cross channel, which exist in channelized process, we as well as research the corresponding solution. Next, the relevant technologies of digital channelized FPGA realizing are studied, such as orthogonal digital down-converter, filter technology, etc,specially studies the implementation of digital FIR filter based on FPGA, Analyzes different implementations based on FPGA,clock-selective-computing algorithm fitting for FIR decimation filter is used at digital down-conversion ,this FIR filter works in reducing the rate of multiplier and the data of computation, Consideration from the complexity,the direct-type FIR filter is used at polyphase filtering of digital channelized receiver.Finally,the program of the system is simulated based on Matlab and FPGA, the simulation analysis verify the correctness of the method, meet the project requirements.