Implementation, Performance Study And Optimization On Different Platforms For DSP Algorithms

Speed and power are two crucial aspects for digital processing, because the amount of information needed to be transformed and processed is growing fast, and at the same time power consumption is drawing more attention with the growth of device density. As a result, Digital signal processing (DSP) algorithms and their implementation are worth studying and optimizing, in order to make them more efficient and attractive.The transform from an algorithm to operation consists of two levels:the higher control and data flow level which can be considered as the algorithm level and the lower implementation level. Both of the two levels can influence the performance of an algorithm. Besides, the data flow and control mechanism of one DSP algorithm may be totally different from those of another, leading to the structure of their implementations are far different from each other. For the purpose of speed and power optimization, this thesis works on different optimization methods for different platform implementation, as well as the implementation of three DSP algorithms and their comparison of speed and power.Three typical DSP algorithms-FFT, FIR and Viterbi decoding which are very commonly used in practically applications such as wireless communication, audio & video systems, Internet and so on, are studied in this thesis. The three algorithms are mapped to three common platforms-Software, FPGA and ASIC, respectively. Based on the above work, a novel platform called DRRA (Dynamically Reconfigurable Resources Array) exploited in KTH is deeply studied. In addition, some conclusions on DSP algorithms implementation are drawn as well. Besides, the FPGA measurement method is investigated in this work. Two kinds of testbench are designed, and the measurement results and their errors are derived from mathematics respectively.