Design And Implementation Of Technology Mapping Algorithm In LUT-Based FPGA

Technology Mapping(TM), which transforms a technology independent structure into a particular technology specification, is the most important part of development environment for Field Programmable Gate Array (FPGA) supporting software and its result has made a direct impact on the performance (quality, cost, etc.) of implemented circuit chips. In recent years, how to improve the performance of TM has become a hot research area.In this thesis, the basic theory of FPGA based on Lookup-Table (LUT) and the development process of its supporting software are first introduced. Further, a detailed analysis of the theory and mapping process of TM for FPGA is made, and the well-known mapping algorithms of TM and its key techniques are given in detail. Labeling process is the kernel of TM. By analyzing and studying of the TM algorithm CUT-MAP, this thesis puts forward an improved labeling algorithm, which improves the performance of TM to a certain extent. Finally, this thesis presents a TM algorithm named XDTechMap based on Network Flow and discusses its two phases:labeling and covering respectively in detail. At the same time, a detailed description of the algorithm XDTechMap and the pseudocode of its implement are given too. Experimental results show that this algorithm has a good performance in delay and area optimization.