Optimization On Technology Mapping For LUT-Based FPGA

Technology mapping is an important step in the development of FPGA supporting softwares. It transforms a technology independent structure into a particular technology specification which directly affects the performance and cost of the final circuits. Accordingly, this thesis focuses on optimizing algorithms for technology mapping of FPGA.As the crucial and time-consuming step in technology mapping, cut enumeration is used for preparing candidate cuts for cuts selection in the next step. By the analysis of the existing algorithms, a new algorithm, named XDPriorCutMap, based on priority cuts is proposed in this thesis. The algorithm computes a small number cuts and sorts the candidate cuts by a sorting function concerning the optimization goal, and then selects the best cut and stores it at the node. By avoiding the enumeration of all the cuts in the traditional mapping, the new algorithm not only optimizes the depth of circuits, but also saves memory and running times.Finally, concerning to a new developing direction of FPGA, Hybrid FPGA, a technology mapping algorithm based on depth and area is proposed and how black boxes in the optimization step can be handled is also presented.