Research On FPGA Technology Mapping Algorithm

FPGA technology mapping transforms a network of technology-independent logic gates into one comprised of logic cells in the target FPGA architectures. In a typical FPGA design flow, mapping is the last step in which the design is transformed. As a result, technology mapping has a significant impact on the quality (area, performance, power, etc.) of the final implementation. The typical mapping aims at the network coverage using LUT, to achieve the optimization of area and timing performance. Currently, the CAD algorithm is facing numerous new challenges with the advancement of FPGA design technology. The thesis focuses on FPGA technology mapping algorithm researching on area/timing performance and heterogeneous mapping, it also presents an automatic testing system and methodology which helps software designers find out the problems in their CAD algorithms.We first introduce the traditional structural mapping algorithms and study the main improvements including DAOmap, ABC tool and FDmap. The thesis shows the differences between these algorithms, and presents a new mapping algorithm based on function classification and bloom filter, the new algorithm reduces the size of matching library to 5% compared to the original one. Combined with the dynamic learning filter strategy, it can also reduce 15% LUT number.We also present an automatic testing system and methodology based on JTAG, which will do a regression test each time when the software designers change their algorithms. The system will find out whether the slightly changed algorithms have a problem, in this way, the CAD software will be more robust than ever.