Research On Mapping-based Optimization Technology For NoC

With the rapid development of artificial intelligence,big data,cloud computing,and other fields,the demand for processor performance is increasing.The number of IP cores in So C(System on Chip)is increasing,and the scale of network-on-chip is also increasing.There are many issues,such as communication power consumption and network congestion,which decrease the performance of No C,rapidly.In recent years,research on the optimization of No C has become one of the research hotspots in related fields.Therefore,this thesis forces on the optimization of No C,which includes No C mapping,the No C optimization method,and No C simulators.This paper presents a mapping-based optimization technology for network-on-chip.The main contents of this paper include:1.A novel genetic-based hyper-heuristic algorithmA novel genetic-based hyper-heuristic algorithm(GHA)is proposed as the core algorithm of the No C mapping.This algorithm consists of a bottom-level algorithm which includes a variety of genetic operators and a top-level algorithm which selects suitable operators through a‘reward' mechanism.As this algorithm can select suitable operators automatically during the mapping process,it noticeably improves convergence speed and demonstrates excellent stability.Compared to state-of-the-art mapping algorithms,GHA produces improved mapping results with less time,especially when the size of No C is large.2.A mapping-based optimization technology for network-on-chipAccording to the characteristics of routing structure and communication mode of network on chip,a comprehensive evaluation model of network-on-chip(including delay,power consumption,temperature,etc.)is established.The Standard Architecture libraries(including Mesh,Torus,Ring,Spidergon)are established.According to the given application and design constraints,the appropriate standard architecture is selected as the basic architecture,and the optimal mapping scheme is obtained by mapping optimization technology.Based on the optimal mapping scheme,the information of IP core layout,the communication volume through routers and links,the length of links are calculated.The technologies of deleting invalid routes and links,increasing long-range links,optimizing topology,low power coding,and low swing circuits are adopted.Based on the target of area,power consumption,delay,and temperature,the architecture of the system is optimized.Finally,a network-on-chip architecture with excellent performance is obtained.3.A novel FPGA-based NoC simulatorWe proposed a fast and flexible FPGA-based No C simulator-SRNo C.Compared to the state-of-the-art FPGA-based No C Simulators,SRNo C adopts a new simulation architecture(switch-router architecture),in which virtual boundary technology is adapted to improve the simulation speed further.At the same time,switch-router architecture can support on-line configurability of network-on-chip topology,which avoids re-synthesization and reimplementation.Because we integrate the power consumption model and temperature model into SRNo C.SRNo C can support not only the simulation of the delay but also the simulation of the power consumption and temperature.