Technology Mapping Of Delay And Area Optimization On Local ROBDD

FPGA EDA support software mainly consists of logic synthesis, technologymapping, placement, routing, simulation, etc. As one of the most important steps,Technology mapping will directly affects the cost and performance of the final circuit.This article is to achieve technology mapping section.Technology mapping can be divided into two parts：the logic optimization andstructural optimization. The task of the logic optimization is to decompose the circuitefficiently, so as to satisfy the K-LUT requirement that the number of input node ofevery unit of circuit is less than or equal to K. The next step is structural optimization.The goal of the structural optimization is to optimize the area and delay of the circuitafter logic optimization. At present, the efficiency of logic optimization also needs to beimproved, and how to find the balance between area and delay becomes an importantproblem for structural optimization.For the logic optimization, this paper proposes an algorithm use the ROBDDwhich is one of the most effective forms of circuit expression to express circuit. Thispaper proposes the idea of minimizing Local ROBDD and using domain operation ofROBDD to achieve the purpose of efficient decomposition circuit and also providegreater flexibility for the next step. For the structural optimization, based on theclassical delay optimization algorithm FlowMap, this paper proposes the idea that usesmin-cost and min-height division for the node on critical path, and uses min-costdivision for the node on non-critical path, so as to optimize the area and delay of thecircuit at the same time.