The Design And Analysis Of A Kind Of NOC Router

With the rapid development of IC design technology and manufacture process, not only the integrated scale and the clock frequency are increasing fast, but also the system complexity and design difficulty are growing greatly. Traditional SOC development has met many challenges: the communication skill becomes the bottleneck; physical design's complexity increases; design for test restricted the system; and the implementation of synchronicities becomes more and more difficult, etc. Facing with the challenges, as a new solution, the concept of network on chip (NOC) was proposed. This paper discusses about the design and analysis of the router network architecture, which is the key part of a NOC system. Along with the related projects, these following points are discussed in the paper:Firstly I introduced the background and technology of NOC theory, including the structure, algorithm, and communication protocol.Then I illustrated the detail design of the router node. Base on the traditional X5 router structure, I put forward a new X6 router structure with a connected memory module, and then I did the functional verification. On Altera FPGA platform, the whole design was implemented and the corresponding performance analysis was made.Finally, with the connection to Nios II multi-processor system, I made comparative analysis of the throughputs respectively on X5 and X6 systems.Through the analysis, design and verification above, an efficient NOC router architecture has been presented to meet the requirement of our project, and also a multi-processor simulation platform has been made for some applications. The content in my paper is limited, but as a preliminary research and exploration, it's expected to lay the foundation for further improvement design and complicated application.