Research And Implementation Of The Interconnection Network Of X Stream Media Processor

Nowadays the performances of most parallel processor systems are restricted by their communications or their interconnection modes, not by their operation units. With the development of technology, memorizers and processors are getting faster. But the pin density and the interconnection density of processors are difficult to grow. The communication frequency among processors is far behind the internal clock frequency of modern processors. All of these equations make the interconnection techniques become the key factor of the future parallel processors.The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size. It commonly is the bottle-neck of the parallel processor to increase the frequency and lower the achievement. Now the investigation and implementation of high performance interconnection network have become the hot point in the world.Stream processor is a kind of specific processor, its application mainly face the domain in denseness calculation. Treated as the acceleration unit, it is used to develop the calculation performance towards stream data. In X stream processor system, many stream processor chips constitute an array system. It can handle the application needs in parallel calculation more efficiency.This article research and implement the interconnection network based on X stream processor minutely. The frequency in this design is more than 500MHZ through simulation and synthesis. The latency in network router is 6 clocks time, and the throughput reach the value of 8GB/S. It matches the demand of performance in X stream processor.The NC adopts the planar rounding net to be the implementation of structure, transmits the data in 4 directions. And the router arithmetic is fixation. NC has 2 internal interfaces to communicate with stream data and system message separately. The router adopts the structure of crossbar. Because the key factor in NC performance is the long latency in crossbar, this article researches the entire crossbar generally. NR adopts 2 combinatorial 3×3 crossbars instead of the 5×5 crossbar. And design the router arithmetic carefully to match the demand of shorter the logic levels and lower the key path latency.The whole design has succeeded in the test of large data input, operation in each instruction, border condition and every random data vector. The code coverage has reached the percentage of 100%. At the same time, this design used the stream C language to test NC in system platform. X stream processor has taped out successfully. The processor is under testing now. Consequence of the original verification shows that NC works functionally and its performance meets the demand.