Network Processor-based Programmable Router Technology Research

Network Processor is a programmable processor, which can be used in disposing the data through network. It has a wide applying field, and compared with the router based On GPP (General purpose processor) as well as the router based on ASIC(Application Specific Integrated Circuit), the router based on Network processor has both high speed and high flexibility.IXP Network Processor family is the product of Intel company. Within IXP Network Processor family, IXP1200 Network Processor is the first Network Processor type manufactured by Intel company. It is composed of a Strongarm processor, six microengine processor, SRAM unit, SDRAM unit, and PCI bus unit. Every microengine has four hardware threads, and the contrl of microengine switches from one thread to another thread by using non-preemptive hardware thread arbiter swaps. By paralleling among the threads, IXP1200 Network Processor hides the delay caused by memory operations.To IXP1200 Network Processor, receiving packet and transmitting packet are finished by Receive State Machine and Transmit State Machine in IX bus separately.VERA theory is proposed by network research group of department of computer science in Princeton university. It divides the router in three components: router abstraction, hardware abstraction and distributed operating system, router abstrac -tion is mainly used in realizing router function extension. Hardware abstraction is mainly used for providing a interface independent hardware devices. Distributed operating system is used for providing a execution environment to transmiting function which ties router abstraction and hardware abstraction together. The ways of processor hierarchy and Transparent Dynamic Code Injection are very important in VERA theory. Processor hierarchy are used for guaranty that bottom hierarchy can provide line speed and high hierarchy can have enough cycles to process data needed a large amount of transaction times. Transparent Dynamic Code Injection mechanism embodies the flexibility in router based on Network Processor, and it can be used for dynamically changing the codes stored in Network Processor.In this paper,IXP1200 multiports processing platform is designed for realizing that receive Ethernet type frames, process them, and transmit them. And , the paper describes the realization of a 16-port processing platform built by IXP1200. By multithread and paralleling mechanism in IXP1200, this 16-port processing platform can realize high-speed and high-efficient port receiving and transmiting. During the receiving stage, there are different processings among the SOP, Middle MP , and EOP. Transmitting stage is fulfilled by transmitting scheduler threads and transmitting fill threads. Assignment tasks are finished by transmit scheduler threads , while transmitting fill threads mainly finish the function that copy data from SDRAM to TFIFO . Also, transmitting MPs are divided into SOP, Middle MP, and EOP, which undergo different processings.