Design Of Multi-core Verification Platform & Research On Turbo Codec Technology

With the development of the mobile communication technologies, LTE has taken the place of 3G and become the latest mobile communication standard; Meanwhile the real-time transmission of massive audio and video information has become a reality. LTE can reach a peak throughput of 50Mbps in an uplink and 100Mbps in a downlink respectively, which is improving with the advanced LTE standard accordingly., Baseband solutions in 2G and 3G stage were only based on single-core DSP. Since the need of the data-processing capacity is increasing, the computing bottleneck of LTE concentrates on Orthogonal Frequency Division Multiplexing(OFDM), Multiple Input Multiple Output(MIMO) and Turbo codec, which means the traditional single-core processor can hardly meet the LTE's requirement of data processing. Regarding to the LTE baseband chip, multi-core DSP solution is mostly appreciated in the market presently.Verification plays the most important role in the multi-core DSP design flow. Therein FPGA verification, which can provide an actual chip timing and shorten the simulation time, has become one of the key methods. Based on the study of Mesh and crossbar structure, four Altera EP2S180F1020C5N chips were used to implement the multi-core FPGA verification platform in this paper.The contents cover the following aspects:1. The model of multi-core processors, multi-core verification and verification platform design technology have been researched and they were used as the theoretical basis of multi-core FPGA verification platform design.2. The multi-core FPGA verification platform based on four EP2S180F1020C5N chips has been implemented on a Print Circuit Board(PCB) by designing the power, configuration circuit, peripheral, I/O and interconnect structure respectively.3. The section of Turbo codec in LTE protocol have been studied, and floating-point and fixed-point simulation of LTE Turbo codec as well as the implementation for the fixed-point processing have been completed, meanwhile recommendations for DSP instruction set design have been proposed.4. FPGA resource utilization of a single core was analyzed firstly. Then preliminary estimate of Turbo decoding computation was carried out to assess the feasibility of Easecore's FPGA verificaition on multi-core verification platform. Finally the test solution of Turbo decoding on Easecore was proposed.