Verification Research For Vector Scalar Fixed-point Floating-point Conversion Unit Of Microprocessor

With integrated circuit entering the age of More Moore,the scale of integrated circuit is increasingly growing,the function increasingly complicated,verification accounts for 70%in chip R&D cycle,while the traditional way of direct verification cannot meet the engineering requirements.The UVM verification methodology of System Verilog was a mainstream and proposed by engineers who expect to shorten verification cycle by improving code repetition rate,randomizing test stimulus and automating result comparing.However,in some subjects with huge data volume,UVM method also hits bottlenecks.Engineers have shifted their attention from simulation to formal verification and expect to raise verification efficiency and assure its completeness.The verification object of this paper is the customized microprocessor vector and scalar floating-point fix-point convert unit based on POWER ISA.It has complicated functions and there are no similar verification schemes for reference.In order to solve the problem,this paper conducts careful study of IEEE754 Standard and POWER ISA special regulations of floating-point number and architecture base of instruction execution.Based on this,this paper formulates simulation verification scheme complemented by formal verification.Vector and scalar floating-point fix-point convert unit is characterized by many data types and large data volume.The maximum of single instruction input change can reach 2¹³³situations.It is not feasible to test all the input in the project and it also poses a great challenge to the completeness of verification.In order to solve the problem,this paper conducts in-depth analysis of each instruction operation process in a variety of operation modes.By means of equivalent class decomposition method and boundary value decomposition method,the paper concludes the feature of each instruction.Instruction source operand constraint is set in accordance with the feature.Thus less test cases are used to test all the features as well as the project feasibility and verification effect can be ensured.In addition,the method of equivalence checking is simply explored and its advantages and disadvantages are summed up.The verification platform needs to simulate the instruction execution environment,including the decoding function,source operand register and floating-point status and control register function,and the synchronization of the three mentioned above.In order to solve the problem,this paper adopts Universal Verification Methodology Component to divide and simulate each module function as well as make the platform better organized and maintained.After the verification is made according to the verification scheme,the code coverage of simulation verification reaches 97%and the function coverage reaches 100%.A reasonable explanation is given for the uncovered code coverage.Some typical instructions in formal verification pass the Equivalence Checking and achieve ideal verification effect.