Design And Verification Technology Of A 16-bit DSP IP Core

As the critical signal processing chip, DSP is developed rapidly with the development of the signal processing technology. A 16-bit fixed-point DSP designed in this paper has a Harvard memory structure, a four stage instruction pipeline in which data and program is accessed by DAG and PAG respectively. Instruction decoding is completed by pipe-line controller while instruction execution and the operation of data are performed by CALU, PLU and memory mapped registers. Clock generation, idle control and external interrupt synchronization is carried out by clock control block. The DSP peripherals, including serial port, TDM serial port, timer, wait-state generator, interrupt generator and memory mapped I/O ports, are designed to implement the communication and control to external data. Using ModelSim and EP2S60 development board, the simulation and the FPGA verification of design are performed, the results of which indicate that the function of design met the requirement of the function.