Design And Research Of A16-bit-fixed-point DSP Core

In recent years, to meet requirement for the continuous development of informationtechnology, digital signal processing technoly emerges with rapid development. In manyaspects, such as digital communication,signal processing and image processing, DSP hasbeen considered to be the most innovative electronic products, with its many advantages inprogammble, high precison and stability, easy to integret in large scale, and implementadaptive algorithm. Compared with floating-point DSP,16-bit fixed point typesignificantly characterized by its low cost and power and has widely applied in DSP area.Relevant background and basic conceptions are firstly introduced in this article, Onthe basis of the therotical knowledge, the design idea of the general DSP core are presented,including the fundamental parts, bus structure, basic pipelining conception and pipelinetechnology that adopted by general DSP core. According to the conversed analysis processof the intergrated circuits, TMS320LF2407A chip is reversed analyzed and variousmodules of chip are verified with the initial simulation. Furthermore, overall function ofthe DSP core are also verified through the simulation. Under the premise of workingproperly, the design method is summarized in this paper which contains the bus and coremodule design the comprehensive analysis of pipelining implement, instruction and datasteam, and interrupt processing of the DSP core.Moreover, the function of each modulesare analyzed in detail and the description of the complete design plan is eventually putforwared. Finally, the conception of low-power technology is proposed, including themethord to achieve low-power and several improvents on the low-power dissipation ofDSP core design.The research in this paper is oringinated from the TMS320LF2407A chip surppotedby the project from Beijing Huaxi silicon corporation. Combined with BCD0.18technique,reverse analysis of the chip is completed at first. Furthermore, the analysis of DSP core isconducted through top-down design. After that, many aspects of the DSP core performanceare realized and verified with the utilization of Modelsim simulating environment, suchas instruction cycle, addressing mode, logic fuction and power consumption. The results indicate that the DSP core can execute correctly all the180instructions with maximumclock operation frequency of12.5MHZ and complete high-speed algorithms within singlemachine cycle with maximum power dissipation of only26mw, dramatically enhance theDSP operation efficiency. When the layout design factors are taken into comprehensiveconsideration, the layout design is eventually accomplished.