Soft Bit Detection Techniques And Fixed-Point Number Decoding For Binary Turbo-Coded Transmission Systems With High Order Modulation

Since the Turbo coder was proposed in 1993, it has been widely used in all kinds of wireless communication systems because of its excellent performance, which is close to the Shannon limit. Turbo-encoded transmission system simply combines binary turbo code with high-order modulation (M-PSK/M-QAM) schemes. In the Turbo decoder of that system, the input is soft bit information, so this thesis is aimed at researching on the soft bit detection algorithm, the performance of which are simulated in Turbo-encoded transmission system.Firstly, the thesis briefly introduces the development of digital communication system and channel coder, mainly introduce status and significance of the binary turbo coder and the bit detected algorithm. Secondly, the thesis also introduces the principle of the binary turbo-coded transmission systems with high-order modulations.Then, based on log likelihood ratio (LLR) Log-MAP algorithm and simplified Max-Log MAP algorithm, and 8PSK,16QAM,16QAM,64QAM modulation respectively specific soft bit detection algorithms are described in detail. The influence of these bit detection algorithms on the BER/FER performance are analyzed. Results show the decoding BER/FER performance of those 8PSK,16PSK,16QAand 64QAM modulation specific soft bit detection algorithms are far better than Log-MAP algorithm,which is based on maximum a posterior estimation of the log likelihood ratio, and their computation complexity are much lower than Max-Log-MAP soft bit detection algorithm.Finally, the fixed-point number decoding of turbo-encoded transmission system is studied, introduces the fixed decimal fraction bit-width and integer bit-width number ranges, and simulates and analyzes the performance of fixed decimal fraction bit-width and integer bit-width number ranges in the turbo coding and transmission system. Different fixed-pointed binary bits wide(including the decimal part and integer part) on the decoding performance is simulated and analyzed, and accordingly a suitable bit wide value is gained, which comes to 3-4 bits on integer part and 4-6 bits on decimal part.