Design And Implementation Of Intra Prediction And Loop Filter Module In AVS Video Encoder

With the rapid development of modern communication, multimedia and network technology, obtain information become more urgent for people. Video is one of the important ways to access the outside world information. Video transmission informative require high bandwidth, therefore, how to effectively compress video information is great important.AVS (Audio Video coding Standard) which is set by the Chinese Audio Video coding Standard panel is a new generation Video compression Standard. AVS has the following advantage:clarity intellectual property rights, simple technical solution, advanced performance, and low implementation cost. Because of high quality transmission under limited bandwidth and low cost, AVS has a broad application prospect. However, encoder algorithm is complicated. It is difficult to meet the requirements of real-time encoding with the software implementation. In this paper, by researching the basic grade of AVS encoder hardware implementation of intra prediction module and loop filter module, the problems in the design of effective solution is proposed. In this paper, the main work is as follows.First, design AVS intra prediction module. Change trend direction to reduce the candidate intra prediction model by the optimal prediction model correlation between adjacent block and block pixels. Reference sample management module is used to solve the memory bandwidth limited data throughput and affect the coding efficiency. Simplify the reference data selection mechanism throuth predict the core unit of PE forecast cell array. Realise complicated Plane model by pulse array and shift instead of multiplication.Second, design AVS loop filter module. To reduce the critical path delay by structure of level 5 pipelines, assign the complex filtering calculation of path delay on 5 clock cycles. Make full use of the data correlation and improve the filtering order, make filtering centralized data processing, decrease the number of access for filtering sub-block. For the filter can deal with two kinds of boundary, design the staging and transpose registers. Improve the filtering efficiency by designing parameter calculation module. Improve the filtering speed by designing filter cell parallel processing.Third, Use the top-down design method. Complete the RTL design of intra prediction module and loop filter module by Verilog HDL language. Do simulation using the ModelSim. Finally analyze the result of the design. The results show that the above two modules fully satisfies the requirement of real-time 4 cif format video coding.