Study On Inter-Frame Prediction Technologies Of High-Definition Video Encoder Chip Design

Inter-Prediction is one of the key technologies in high efficient video coding standard, such as H.264/AVC and AVS. It eliminates the redundancy in video data by taking use of the relativity of neighboring frames to compress video content. With the development of high definition video content and new technologies, the complexity is increasing dramatically, leading more difficulty in video codec chip design.The thesis focuses on hardware design of inter-prediction in H.264/AVC and AVS. It discusses the inter-prediction technologies in detail, including resource constraint, hardware-oriented algorithm design, bus tasks and memory storage arrangement, architecture design and optimization, and so on.By analyzing the coding modes in high definition video sequences, we propose a two-level mode decision strategy. It reduces the complexity to a large extent with little performance loss. Benefit from this strategy, the pipeline structure of the encoder is optimized and a sharable architecture of FME, SME and LMC is recommended, which improves the implementation efficiency greatly.To meet the bandwidth constraint, we adopt (0,0) as the search center of motion estimation, and eliminates the data access for FME, SME and LMC by data reusing on-chip. Furthermore, off-chip memory format design is analyzed in detail to improve the bus efficiency. As a result, comparing with other methods, we decrease the data access on the off-chip bus by 70%.Finally, the architectures of inter-prediction modules are proposed, including integer motion estimation (IME), which is more efficient than the references; the sharable architecture of FME/SME/LMC, which can be used by different tasks in both H.264/AVC and AVS; the chroma motion compensation module, which achieves about 20% decrease of logic resource cost. In the end, all modules are simulated and synthesized, and the result meets the design target.