The Design Of Loop Filter Module In A Multi-mode Video Decoder Chip

With the development of semi-conductor and computer technology, the digital and high definition of audio-video products have become the trend of the consumer electronic, nowadays high definition television has become the trend of Digital TV and a lot of research efforts have been made. At present, the dominating new standards used for HDTV video compression are H.264/AVC and AVS, both of them adopt block-based integer transform, quantisation and block-based motion compesation (MC), which will be the source of blocking artifacts and will reduce the subjective video quality and compression performace. So they adopt a filter in motion-compensation loop as a post-processing to remove blocking artifacts.On the base of analysis the deblocking loop filter algorithm, this paper proposes an efficient architecture to realize the deblocking loop filter in H.264/AVC and AVS. It is adaptive in three levels: Edge-Level, Slice-Level, Sample-Level, which leads very slow speed. Our design emphasizes on using parallel processing technology from multi-level to improve speed, including pipelining design, data-flow drive strategy and algorithmic parallelism design.As a sub-module in multi-mode video decoder chip, our design supports the reuse of H.264/AVC and AVS. The reuseable technology saves the hardware resource. In addition, only one edge filter is used for both vertical filtering and horizontal filtering in our design by proper data storage and attemper, this reusing strategy reduces the resource cost.The simulation result shows that this architecture can fulfill adaptive deblocking loop filter in two standards functionally.The organization of this paper is as follows.In chapter one it briefly introduces the concept of the video compression and the basic tools of video codec, including entropy encoding, motion compesation and post-processing etc. In chapter two, it discusses the algorithm of deblocking loop filter in H.264/AVC and AVS respectively. In chapter three, based on the similarities and differences of deblocking loop filter in the two standards, it proposes an efficient reusing design. In chapter four it proposes a hardware implementation architecture which supports reusing design, and further more it probes into the parallel processing strategy and analyses there applications in our design in depth. In chapter five it accomplishs the simulation and synthesis for RTL model, and then gives the result. In chapter six, it makes the conclusion.