The Research Of Key Technique On Instruction Control Unit In The X-Microprocessor

In this paper, we give a design of a two-issue superscalar processor's(X processor) instruction control unit, basing on analysis and research of x86 processor instructions. The verification of key units is also given.Instruction control unit in X general microprocessor will perform following functions:1. Select 2 instructions from instruction streams which get from instruction cache;2. Perform instruction decoding, paring, dependency checking, dispatching.X general microprocessor adopt complex instruction set, the instruction vary in length . So it is very difficult for us to select two proper instructions from instruction stream. To solve this problem, first we must decode instruction length. Over the entire process of instruction controller's design, we put instruction length decoding stage before instruction fetching. This is to say, instruction length decoding and fetching, is performed simultaneously. ? This design method is more accurate than the method based on length guess.Accurate branch prediction is required to achieve high performancd in deeply pipelined wide-issue processors. To improve branch prediction accuracy, we introduced branch prediction buffer based on two level adaptive branch prediction algorithm in X processor. Its main consideration is to break branch history information into two level table: the first level table is actual branch history information table; the second level table is prediction branch history information table, formed by two level adaptive branch prediction algorithm.In the end, the verification of main module of our design is performed.