The Study Of Simultaneous Multithreading In VLIW Processors

Since Tullsen proposed simultaneous multithreading technology based on superscalar processors at 1995, it has become a focus in the field of processor architecture. A SMT processor permits multiple threads (logical processors) to share the same set of computational units. It not only develops thread level parallelism, but also avoids the cost of context switch.Due to insufficient instruction level parallelism in applications, the capability of compiler, or kinds of dynamic events in pipeline, VLIW processors are not effectively utilized. Combining VLIW and SMT technology provides a new method to improve further the performance of a VLIW processor.This dissertation focuses on the microarchitecture design and optimization of SMT VLIW processors, analyses two kinds of timing restrictions caused by the execution semantics of VLIW architecture, investigates methods to break these restrictions, and proposes a kind of SMT microarchitecture, MOSI, for VLIW processors. The dissertation proposes new optimization methods, since characteristics of VLIW architecture prevent SMT VLIW processor from achieving higher performance. This dissertation presents a mechanism for controlling each thread's performance in SMT processors, and implements a dual-thread MOSI VLIW processor prototype. The main contributions are as follows:1. The dissertation revises replay buffer mechanism, which implements precise interrupt in NUAL processors, proposed by Rudd, reduces hardware cost of this mechanism.2. This dissertation proposes a kind of SMT VLIW microarchitecture, MOSI, which breaks timing restrictions caused by VLIW execution semantics. It not only satisfies the basic requirement of SMT technology, but also reduces hardware costs.3. Based on MOSI microarchitecture, the dissertation presents an instruction transfer technology, which eliminates the defect of static functional unit assignment. It can automatically balance workloads among functional units, so improves the utilization of functional units and the throughput of SMT VLIW processors.4. This dissertation proposes a kind of non-blocking pipeline control mechanism on MOSI microarchitecture. This mechanism reduces invalid instruction requests in instruction fetch unit, so improves the throughput of instruction fetch unit and the whole processor.5. To regulate the performance of each thread, this dissertation presents a mechanism that makes each thread run at a predefined speed ratio by dynamic resources allocation.6. This dissertation designs and implements a dual-thread VLIW prototype based on MOSI microarchitecture. By logical synthesis, timing analysis and performance evaluation, it shows hardware cost and time delay of the prototype. This prototype achieves 12 to 26% performance speedup when time delay introduced by MOSI microarchitecture is concerned.The research in the dissertation provides a theoretical and practical solution for implementing SMT technology based on VLIW processors, and the production can be used to investigate further how to improve system throughput of a SMT VLIW processor.