The Research And Simulation Of The Algorithm Of AGC In DVB-C Receiver

Digital Television (DTV) is the future development direction of the broadcast television system. DVB-C, the standard of digital television cable transmission, has been accepted by most countries. The research and development of DVB-C channel demodulation chip are very important to the accumulation of technologies about digital television chips in our country, as well as boost the development of digital television industries.This paper will introduce the principle of the DVB-C series standards firstly, and then the sketchy design of the system will be stated. At last, the software and hardware parts of the digital AGC and analog AGC will be discussed in detail, especially its design with FPGA design.What I have done in the project is listed below:A) Collect the information and paper on DVB-C and get familiar with the total DVB-C system.B) Design the total scheme of QAM receiver based on DVB-C.C) Create the simulation data received of QAM receiver. Complete the design of digital AGC and analog AGC of software simulation system.D) Use Verilog HDL language to implement digital AGC and analog AGC programming -. testing and debugging.E) Take part in software and hardware system testing and debugging.It is proved through the FPGA validation that the modules described in this thesis can well cooperate with other modules in the system and the final FPGA chip can successfully recover digital television signals and reach DVB-C system performance standards.