Algorithm And Circuit Design Of Floating-Point Division And Square Root

The task is to develop a high-speed unit of floating-point division andsquare-root for FPU which build in LX1164 general CPU. Today, a important guideline for evaluating a CPU's performance is itsfloating-point operation capability. Floating-point division unit is a main compo-nent of FPU. This paper discusses some algorithm of division and square root. Inmy design, I use improved Newton algorithm for square root and Goldschmidt al-gorithm for division. To hardware implementation ,I use ASIC design method and use advancedEDA tools to design logic and simulator. This unit is absolutely compatible withIEEE 754. In this unit , we adopt reconfiguring technology.