Verification Of Processor Floating-point Division/Square Root Unit Based On UVM

With the development of science and technology,the requirement of the processor performance continue to be improved,including military,aviation,medical and other fields.The complexity of the processor chip and circuit scale is growing,the difficulty of corresponding verification is also increasing.To ensure the correctness of processor chip design is particularly important.In the traditional chip research and development process,it spents much more resources and time to verify the work,which is further increasing.How to improve the efficiency and quality of verification has become one of important research direction of chip research and development.It is academic significance and application value to solve the bottleneck of verification,which is a high degree of automation,good verification and good reusability.Based on the study of IEEE 754 standard and floating point division method,a detailed executable verification plan is designed according to the design spec,the test function points are analyzed,and a complete coverage model is established.The verification platform stores the source operand,instruction decode control signal and register control signal of the 12 units of the arithmetic unit into the uvm_sequence_item transaction class,and establishes the corresponding UVC.Then,base on the virtual sequence mechanism of UVM,five kinds of test incentives are designed to verify the different stages.The three kinds of transaction classes are driven synchronously to the DUT and the reference model.The output is divided into 128 bit floating point operation.The result and the register status signal are collected and sent to the scoreboard for comparison.Cadence's incisive is used to compile and simulate to complete this verification platform,and v Manager is used for authentication and management,so that verification can be done in a qualitative,fast and orderly manner,and the bug statistics is identified.During the regression testing phase of the verification,statistics and collection coverage are mapped to the verification plan and analyzed based on the metric,adjusted for verification strategies,and developed specific orientation test incentives to achieve the desired coverage.In addition,through the top-level module of the hierarchical design and interface signal classification and packaging,making the platform can be reused in other floating-point operation unit.