Design And Verification Of Floating-point Division/Square Root Unit Based On POWER Architecture

With the rapid development of information technology,various fields are having demands on floating point performance higher and higher,the division and square root,meanwhile,are more complex and quite performance-affected floating-point operations.So,studying floating point division and square root arithmetic operation has great scientific and practical significance.In general IC design process,verification accounts for about 70% of the resources and time,to fully verify a floating-point arithmetic unit faces a greater challenge.If the verification cannot be ensured complete,it will lead to the huge price which is caused like the bug of Intel Pentium processor's floating-point division.Therefore,how to effectively and adequately verify a floating-point arithmetic unit is also a key emphasis in work.The Radix-4 SRT algorithm is adopted to complete a floating-point division/square root arithmetic unit based on POWER instruction set architecture.This paper uses VHDL hardware language and adds the unique SP64(Single Precision 64-bit)format to improve accuracy,it implements the key lookup table in the iteration with as little width as possible while achieving the object of implementing division and square root operations on the same hardware circuit,it has effectively reduced the circuit area.At the same time,UVM is adopted in this paper,and a reusable verification platform of the floating-point division and square root unit is constructed with System Verilog verification language,and it can be perfectly ported to verification of any other floating-point arithmetic unit.An algorithm based on the continued fraction is proposed to solving constraints on the intermediate results of floating-point division and square root operations in this paper.It can effectively generate the boundary test cases,greatly reduce the coverage convergence time and improve the verification efficiency.