Fpga Design Of High Speed Channel Coding And Decoding

The next generation communications wireless system beyond 3G should support high efficient packet data transmission with peak data rate no less than 20. According to the research of new generation cellular mobile communications system around the world, National Mobile Communications Research Laboratory (NCRL) of Southeast University is investigating Generalized Multi-Carrier Time Division Duplex x-Division Multiple Access (GMC-TDD-xDMA) cellular mobile communications transmission technique.And the first stage of demo system based on GMC-TDD-xDMA has been almost completed yet.The research in coding theory and the study in the FPGA design lead to the successful design of channel coding,decoding,mapping, demapping,interleaving,deinterleaving,and the interface module in baseband of this demo system.After function design, timing verification, on board and system-level testing make sure that the baseband link can work stably.Due to the high speed and low area demand,the FPGA design of 256-state Viterbi decoder should be optimized.The parallel structure,overflow protection and the memory management can enhance the Viterbi decoder speed and reduce the area notably.Post simulation result shows that Viterbi decoder can run under after structure optimization.Finally,Float(matlab) and fixed(verilog) simulation plant-form are set up to compare the performance between float and fixed Viterbi decoder under AWGN channel model.The result shows that the perfomance reduce is less than 1.