The Study And Implementation Of LDPC Coding & Decoding Arithmetic

LDPC code is a kind of linear block error-correcting code defined by the sparseparity-check matrix, which has been proved to be a class of Shannon-limit approachingcodes. By using a linear complexity sum-product algorithm, its decoding complexityis much lower than Turbo code, length LDPC codes can even outperform Turbo codes.Due to its advantages, such as lower decoding complexity and lower error ?oor, LDPCcode is coming one of the hottest topics in DVB-S2 and deep space communicationchannel coding theory today. It is receiving more and more attention in academia andthe IT industry, and the application of LDPC code has been put on the agenda.First,the paper gives simple review of the development of channel coding andactuality, introduces the structure of parity-check matrix principle of coding and de-coding. Then FPGA implementation of RU arithmetic and length is carried out afterdeep research and analysis of coding and decoding. According to the nature of binarytree, a new way of ASIC optimization design of LDPC length coding is proposed andlarge quantity of resource is saved. The paper expatiates the principle of CORDICalgorithm and its FPGA implementation with exponential function and hyperbolicarctangent function in LDPC decoding: CORDIC kernel cores and processing unit forthe design, simulation and data analysis, which has important meaning for LDPC code,for it establishes the foundation of implementation using digital VLSI. Meanwhile, onthe basic of the cycles detection theorem of check matrix, a new girth detection isproposed that the check matrix is replaced by transition probability matrix, provingit in theory, the result show girth detection has good results and classifying the stateaccording to simulation.