Design Of The Control Circuit For CMOS Image Sensor And Study Of The Exposure Timing Control

This thesis is one part of the project"Research on the key Technique of Deep Sub-micron High Dynamic, 10M Pixel Level CMOS Image Sensor", which is supported by National Natural Science Foundation of China. Over the past five years, there has been a growing interest in CMOS image sensor due to the demand for miniaturized, low power, and cost effective imaging systems. CMOS image sensor has several advantages over CCD in terms of the opportunity to integrate the sensor with other circuitry on single chip and to reduce packaging costs. CMOS image sensors are becoming increasing important in many application areas such as industrial automation, home applications, car electronics and security systems.In the thesis discuss the system design and implementing method of the controlling circuit of image sensor. The timing functions of parallel exposure mode and roll exposure mode are detailedly narrated and analyzed, and an improved roll exposure mode is introduced based on the mastery of the roll exposure mode. That is the creative works in this thesis. The arithmetic of the new exposure mode is detailedly analyzed. With the new roll exposure mode the exposure time can be adjusted widely and finely, the dynamic range is improved. The structure of sensor array and functional modules is analyzed. Following Top-Down IC design method and the timing relationship of all controlling signals, the design is divided into several sub-modules based on the requirement of the roll exposure mode. Simulation and debug of whole system is completed. The master and slave of IIC are designed to reduce the width of the bus. The design is synthesized by synplify, and the xilinx and FPGA verification is passed. The frequency of the clk is 20M HZ, which is up to par.All the source codes are written in synthesizable Verilog sentences. In the process of writing Verilog source codes, their synthesizability and reliability are considered at first. The design of the sub-modules use synchronous method, which can improve the reliability of the timing functions.