Research On Test Pattern Generation For Stuck-at-fault And Compression Algorithms

Integrated Circuit (IC) test technology is one of the pillar industry of nationaleconomy, which has a significant impact on the IC design, production andmanufacture processes. The project of IC test is pretty vital for the design andmanufacture of IC chips, as any error is likely to result in the failure of the circuit.The earlier we find the failure, the more expenditure we save. Test patterngeneration technology is required to activate the fault in the circuit. What’s more,the huge amount of the test pattern brings in the burden of data transmission andhardware expenditure. Therefore, it is of great importance that the research on testpattern generation and compression is utilized properly.As the commercial ATPG softwares are not ideal for the theoretical research asthey do not provide the original algorithms instructions. Based on actual demand,the dissertation researches on the D-algorithm for test generation and provides away to realize the sequential circuits generation. In addition, an output optimizationalgorithm is proposed and the amount of the test patterns are reduced to a largeextent. This dissertation accomplished the realization for the test pattern generationunder the Visual Studio2008development environment, which makes it possiblethat both combinational and sequential circuit generation are realized, as well asreducing the cost of IC test. In order to verify the effectiveness of the generatedvectors, fault simulation is adopted on the circuits of ISCAS’85and ISCAS’89,with generating the fault coverage. The result reveals that the proposed algorithmachieves100%coverage.In order to reduce the test burden of automatic test equipment (ATE), testvector compression technology is also one of the research areas. The main contentsinclude:(1) As most of the algorithms is for0and1run-length and ignore thecompatible characteristics between adjacent sub-vectors, this dissertation makesfull use of the compatibility among all the sub-vectors to propose a compressionmethod based on the reference vector and the error correcting code which attemptsto generate more compatible fragments, thereby enhancing the compressionefficiency.(2) As there are more hardware storage resources is currently availablein the IC chips, a compression method based on the compatible data block and dictionary is proposed, which makes it possible that the compatibility of adjacentblocks of data and hardware storage resources are fully used. Compared to othercompression methods, the proposed methods can get higher compression efficiency.The compression algorithms are utilized on test patterns generated by Mintest andthe improved D-algorithm, illustrating the best compression efficiency to be95.11%.